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Bibliography

LN00B096

  1. Coleman J. N., Chester E. I., Softley C. I., Kadlec Jiří :  Arithmetic on the European Logarithmic Microprocessor , IEEE Transactions on Computers vol.49, 7 (2000), p. 702-715 [2000]

  1. Kučera Vladimír :  The H_2 control problem for descriptor systems , Preprints of the 16th World Congress of the International Federation of Automatic Control, p. 1-6 , Eds: Horáček P., Šimandl M., Zítek P., IFAC, (Prague 2005) , IFAC World Congress /16./, (Prague, CZ, 03.07.2005-08.07.2005) [2005]
  2. Kafka Leoš, Kielbik R., Matoušek Rudolf, Moreno J. M. :  VPart: An automatic partitioning tool for dynamic reconfiguration. Abstract , FPGA 2005 - ACM/SIGDA Thirteenth International Symposium on Field-Programmable Gate Arrays, p. 263 , Eds: Schmidt H., Wilton S., ACM, (Monterey 2005) , FPGA 2005 /13./, (Monterey, US, 20.02.2005-22.02.2005) [2005]
  3. Šůcha P., Pohl Zdeněk, Hanzálek Zdeněk :  Scheduling of iterative algorithms on FPGA with pipelined arithmetic unit , Real-Time and Embedded Technology and Applications Symposium, p. 404-412, IEEE Real-Time and Embedded Technology and Applications Symposium 2004 /10./, (Toronto, CA, 25.05.2004-28.05.2004) [2004] Download
  4. Matoušek Rudolf, Honzík Petr :  SDIO Interface for the FPSLIC, ÚTIA AV ČR, (Praha 2004) Research Report 2118 [2004]
  5. Pohl Zdeněk, Heřmánek Antonín :  ADPCM IP Cores, ÚTIA AV ČR, (Praha 2004) Research Report 2109 [2004]
  6. Pohl Zdeněk, Heřmánek Antonín :  ADPCM Demo, ÚTIA AV ČR, (Praha 2004) Research Report 2108 [2004]
  7. Schier Jan, Heřmánek Antonín :  Using logarithmic arithmetic to implement the Recursive Least Squares (QR) algorithm in FPGA , Field-Programmable Logic and Applications. 14th International Conference FPL 2004. Proceedings, p. 1149-1151, International Conference FPL 2004 /14./, (Antverp, BE, 30.08.2004-01.09.2004) [2004]
  8. Heřmánek Antonín, Schier Jan, Regalia P. :  Architecture design for FPGA implementation of finite interval CMA , Proceedings of the 12th European Signal Processing Conference, p. 1-4 , Eds: Hlawatsch F., Matz G., Rupp M., EUSIPCO 2004 /12./, (Vienna, AT, 06.09.2004-10.09.2004) [2004]
  9. Schier Jan, Heřmánek Antonín :  FPGA implementation of recursive QR update using LNS arithmetic , Proceedings of the 4th IEEE Benelux Signal Processing Symposium, p. 1-4, SPS 2004 /4./, (Hilvarenbeek, NL, 15.04.2004-16.04.2004) [2004]
  10. Tichý Milan :  HSLA Version 4.0.0a Demo. (Program), ÚTIA AV ČR, (Praha 2003) [2003]
  11. Líčko Miroslav, Matulík Radim, Matoušek Rudolf, Kadlec Jiří :  Prototyping Board for CAK. (Program), ÚTIA AV ČR, (Praha 2003) [2003]
  12. Schier Jan :  QR-RLS - Celoxica RC1000 Demo. (Program), ÚTIA AV ČR, (Praha 2003) [2003]
  13. Líčko Miroslav, Kadlec Jiří :  An Introduction to the Xilinx System Generator. (Program), ÚTIA AV ČR, (Praha 2003) [2003]
  14. Matulík Radim :  GIN - Pocket Notebook with Synthetic Speech Output for the Blind Users. (Program), ÚTIA AV ČR, (Praha 2003) [2003]
  15. Matoušek Rudolf, Líčko Miroslav, Kadlec Jiří :  European Logarithmic Microprocessor. (Program), ÚTIA AV ČR, (Praha 2003) [2003]
  16. Pohl Zdeněk, Schier Jan, Líčko Miroslav, Heřmánek Antonín, Tichý Milan :  Logarithmic arithmetic for real data types and support for Matlab/Simulink based rapid-FPGA-prototyping , Proceedings of the International Parallel and Distributed Processing Symposium. IPDPS 2003, p. 1-6 , Eds: Werner B., IEEE Computer Society Press, (Los Alamitos 2003) , IEEE IPDPS 2003, (Nice, FR, 22.04.2003-26.04.2003) [2003]
  17. Matoušek Rudolf :  Dynamic reconfiguration of FPGAs: a case study , Počítačové Architektury & Diagnostika PAD 2003, p. 17-23 , Eds: Kotásek Z., Růžička R., Sekanina L., VUT, (Brno 2003) , PAD 2003 Počítačové Architektury & Diagnostika, (Zvíkovské Podhradí, CZ, 24.09.2003-26.09.2003) [2003]
  18. Pohl Zdeněk, Kadlec Jiří, Líčko Miroslav, Matoušek Rudolf, Tichý Milan :  Lattice IP Core used in Real-time Lattice Demo on XESS Board. (Program), ÚTIA AV ČR, (Praha 2003) [2003]
  19. Pohl Zdeněk, Kadlec Jiří, Tichý Milan :  RLS Lattice - Celoxica RC200 Demo. (Program), ÚTIA AV ČR, (Praha 2003) [2003]
  20. Líčko Miroslav, Schier Jan :  FPGA Prototyping Using Extensions to MATLAB/Simulink , UK ACM SIGDA 3rd Workshop on Electronic Design Automation, p. 1-3 , Eds: Hettiaratchi S., University of Southampton, (Southampton 2003) , UK ACM SIGDA Workshop on Electronic Design Automation /3./, (Southampton, GB, 11.09.2003-12.09.2003) [2003]
  21. Henrion Didier, Šebek M. :  Polynomial methods and LMI optimization: New robust control functions for the polynomial Toolbox 3.0 , European Control Conference ECC'03, p. 1-6, IFAC, (Cambridge 2003) , European Control Conference ECC'03, (Cambridge, GB, 01.09.2003-04.09.2003) [2003]
  22. Schier Jan, Kadlec Jiří :  Using logarithmic arithmetic for FPGA implementation of the Givens rotations , Proceedings of the Sixth Baiona Workshop on Signal Processing in Communications, p. 199-204 , Eds: Mosquera C., Perez-Gonzales F., Universidade de Vigo, (Vigo 2003) , Baiona Workshop on Signal Processing Communications /6./, (Baiona, ES, 08.09.2003-10.09.2003) [2003]
  23. Líčko Miroslav, Schier Jan, Tichý Milan, Kühl M. :  MATLAB/Simulink based methodology for rapid-FPGA-prototyping , Field-Programmable Logic and Applications. Proceedings of the 13th International Conference, p. 984-987 , Eds: Cheung P. Y. K., Constantinides G. A., de Sousa J. T., Springer, (Berlin 2003) Lecture Notes in Computer Science. vol.2778 , Field-Programmable Logic and Applications /13./, (Lisabon, PT, 01.09.2003-03.09.2003) [2003]
  24. Heřmánek Antonín, Pohl Zdeněk, Kadlec Jiří :  FPGA implementation of the adaptive lattice filter , Field-Programmable Logic and Applications. Proceedings of the 13th International Conference, p. 1095-1098 , Eds: Cheung P. Y. K., Constantinides G. A., de Sousa J. D., Springer, (Berlin 2003) Lecture Notes in Computer Science. vol.2778 , Field Programmable Logic and Applications /13./, (Lisabon, PT, 01.09.2003-03.09.2003) [2003]
  25. Tichý Milan :  HSLA Package version 3.0.0. Matlab HSLA Toolbox 32- and 19-bit TWIN LNS ALU, ÚTIA AV ČR, (Praha 2003) Research Report 2086 [2003]
  26. Pohl Zdeněk, Matoušek Rudolf, Kadlec Jiří, Tichý Milan, Líčko M. :  Lattice adaptive filter implementation for FPGA , FPGA 2003 ACM/SIGDA Eleventh ACM International Symposium on Field-Programmable Gate Arrays, p. 246, ACM, (Monterey 2003) , FPGA 2003, (Monterey, US, 23.02.2003-25.02.2003) [2003]
  27. Líčko Miroslav, Schier Jan, Pohl Zdeněk, Kadlec Jiří, Tichý Milan, Matoušek Rudolf, Heřmánek Antonín :  Logarithmic Arithmetic for Real Data Types and Support for MATLAB/SIMULINK Based Rapid-FPGA-Prototyping, ÚTIA AV ČR, (Praha 2002) Research Report 2069 [2002]
  28. Líčko Miroslav :  Fast Adaptive Controllers, ÚTIA AV ČR, (Praha 2002) Research Report 2068 [2002]
  29. Schier Jan :  Using the System-C library for bit-true simulations in MATLAB , MATLAB 2002. Sborník příspěvků 10. ročníku konference, p. 497-504, VŠCHT, (Praha 2002) , MATLAB 2002, (Praha, CZ, 07.11.2002) [2002]
  30. Pohl Zdeněk, Líčko M. :  Utilization of the HSLA toolbox for the FPGA prototyping , MATLAB 2002. Sborník příspěvků 10. ročníku konference, p. 462-468, VŠCHT, (Praha 2002) , MATLAB 2002, (Praha, CZ, 07.11.2002) [2002]
  31. Líčko Miroslav, Métais B., Tichý Milan, Matoušek Rudolf :  Extension for Xilinx System Generator - logarithmic arithmetic blockset , MATLAB 2002. Sborník příspěvků 10. ročníku konference, p. 280-284, VŠCHT, (Praha 2002) , MATLAB 2002, (Praha, CZ, 07.11.2002) [2002]
  32. Matoušek Rudolf, Líčko Miroslav, Heřmánek Antonín, Softley C. :  Floating-Point-Like Arithmetic for FPGA , POSTER 2002, p. 2, FEL ČVUT, (Praha 2002) , International Student Conference on Electrical Engineering /6./, (Praha, CZ, 23.05.2002) [2002]
  33. Matoušek Rudolf, Tichý Milan, Pohl Zdeněk, Kadlec Jiří, Softley C. :  Logarithmic number system and floating-point arithmetics on FPGA , Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream, p. 627-636 , Eds: Glesner M., Zipf P., Renovell M., Springer, (Berlin 2002) Lecture Notes in Computer Science. vol.2438 , International Conference FPL 2002 /12./, (Montpellier, FR, 02.09.2002-04.09.2002) [2002]
  34. Líčko Miroslav, Tichý Milan, Heřmánek Antonín, Matoušek Rudolf, Pohl Zdeněk :  Prototyping of DSP algorithms on FPGA , POSTER 2002, p. 2, FEL ČVUT, (Praha 2002) , International Student Conference on Electrical Engineering /6./, (Praha, CZ, 23.05.2002) [2002]
  35. Henrion Didier, Šebek M., Kučera V. :  An algorithm for static output feedback simultaneous stabilization of scalar plants , Preprints of the 15th Triennial World Congress of the IFAC , Eds: Camacho E. F., Basanez L., de la Puente J. A., Pergamon, (Oxford 2002) , Triennial World Congress of the IFAC /15./, (Barcelona, ES, 21.07.2002-26.07.2002) [2002]
  36. Hromčík M., Ježek Jan, Šebek M., Hurák Z. :  Polynomial spectral factorization with complex coefficients , Preprints of the 15th Triennial World Congress of the IFAC , Eds: Camacho E. F., Basanez L., de la Puente J. A., Pergamon, (Oxford 2002) , Triennial World Congress of the IFAC /15./, (Barcelona, ES, 21.07.2002-26.07.2002) [2002]
  37. Kadlec Jiří, Tichý Milan, Heřmánek Antonín, Pohl Z., Líčko M. :  Matlab Toolbox for high-level bit-exact emulation of HandelC VHDL FPGA designs , Design, Automation and Test in Europe DATE˙02, p. 264 , Eds: Sciuto D., Kloos C. D., IEEE, (Los Alamitos 2002) , Design, Automation and Test in Europe DATE˙02, (Paris, FR, 04.03.2002-08.03.2002) [2002]
  38. Matoušek R., Pohl Z., Kadlec Jiří, Tichý Milan, Heřmánek Antonín :  Logarithmic arithmetic core based RLS LATTICE implementation , Design, Automation and Test in Europe DATE 02, p. 271 , Eds: Sciuto D., Kloos C. D., IEEE, (Los Alamitos 2002) , Design, Automation and Test in Europe DATE 02, (Paris, FR, 04.03.2002-08.03.2002) [2002]
  39. Kadlec Jiří, Albu F., Softley Ch., Matoušek Rudolf, Heřmánek Antonín :  RLS Lattice for Virtex FPGA using 32-bit and 20-bit Logarithmic Arithmetic, ÚTIA AV ČR, (Praha 2001) Research Report 2036 [2001]
  40. Kadlec Jiří, Heřmánek Antonín, Softley Ch., Matoušek Rudolf, Líčko Miroslav :  32-bit Logarithmic ALU for Handel-C 2.1 and Celoxica DK1, ÚTIA AV ČR, (Praha 2001) Research Report 2037 [2001]
  41. Heřmánek Antonín, Kadlec Jiří, Matoušek Rudolf, Líčko Miroslav, Softley Ch. :  Pipelined Logarithmic 32bit ALU for Celoxica DK1, ÚTIA AV ČR, (Praha 2001) Research Report 2034 [2001]
  42. Coleman J. N., Kadlec Jiří, Matoušek Rudolf, Pohl Zdeněk, Heřmánek Antonín :  The European Logarithmic Microprocessor - a QRD RLS Applications, ÚTIA AV ČR, (Praha 2001) Research Report 2038 [2001]
  43. Albu F., Kadlec Jiří, Matoušek Rudolf, Heřmánek Antonín, Coleman J. N. :  A Comparison of FPGA Implementation of the A Priori Error-Feedback LSL Algorithm using Logarithmic Arithmetic, ÚTIA AV ČR, (Praha 2001) Research Report 2035 [2001]
  44. Matoušek Rudolf, Líčko Miroslav, Heřmánek Antonín, Softley Ch. :  Floating-Point-Like Arithmetic for FPGA, ÚTIA AV ČR, (Praha 2001) Research Report 2039 [2001]
  45. Albu F., Kadlec Jiří, Softley Ch., Matoušek Rudolf, Heřmánek Antonín :  Implementation of Normalized RLS Lattice on Virtex, ÚTIA AV ČR, (Praha 2001) Research Report 2040 [2001]
  46. Kadlec Jiří, Matoušek Rudolf, Heřmánek Antonín, Líčko Miroslav, Softley Ch. :  Logarithmic ALU 32-bit for Handel C 2.1 and Celoxica DK1 , Celoxica User Conference. Proceedings, Celoxica, (Abington 2001) , Celoxica User Conference /1./, (Stratford, GB, 02.04.2001-04.04.2001) [2001] Download
  47. Kadlec Jiří :  Structure estimation for systems described by radial basis functions based on normalized QR filtering , Preprints of the 1st IFAC/IEEE Symposium on System Structure and Control, IFAC, (Prague 2001) , IFAC/IEEE Symposium on System Structure and Control /1./, (Prague, CZ, 29.08.2001-31.08.2001) [2001]
  48. Sugimoto K., Šebek M., Henrion Didier :  Polynomial matrices and recursive QR factorization , Proceedings of the European Control Conference 2001, EUCA, (Porto 2001) , European Control Conference. ECC 2001, (Porto, PT, 04.09.2001-07.09.2001) [2001]
  49. Söderström T., Šebek M., Ježek Jan, Kučera V., Henrion Didier :  An evaluation of algorithms for computing the covariance function of a multivariable ARMA process , Proceedings of the European Control Conference 2001, EUCA, (Porto 2001) , European Control Conference. ECC 2001, (Porto, PT, 04.09.2001-07.09.2001) [2001]
  50. Ježek Jan, Hromčík M., Šebek M. :  New algorithm for spectral factorization and its practical application , Proceedings of the European Control Conference 2001, EUCA, (Porto 2001) , European Control Conference. ECC 2001, (Porto, PT, 04.09.2001-07.09.2001) [2001]
  51. Henrion Didier, Šebek M., Hromčík M. :  On computing the H_infinity-norm of a polynomial matrix fraction , Proceedings of the European Control Conference 2001, EUCA, (Porto 2001) , European Control Conference. ECC 2001, (Porto, PT, 04.09.2001-07.09.2001) [2001]
  52. Henrion Didier, Šebek M., Kučera V. :  LMIs for robust stabilization of systems with ellipsoidal uncertainty , Proceedings of the 13rd International Conference on Process Control, Slovak University of Technology, (Bratislava 2001) , International Conference on Process Control /13./, (Štrbské Pleso, SK, 11.06.2001-14.06.2001) [2001]
  53. Henrion Didier, Sugimoto K., Šebek M. :  Rank-one LMI approach to robust stability of polynomial matrices , Preprints of the 1st IFAC/IEEE Symposium on System Structure and Control, IFAC, (Prague 2001) , IFAC/IEEE Symposium on System Structure and Control /1./, (Prague, CZ, 29.08.2001-31.08.2001) [2001]