Skip to main content
Z. Pohl
Kadlec Jiří, Tichý Milan, Heřmánek Antonín, Pohl Z., Líčko M.
:
Matlab Toolbox for high-level bit-exact emulation of HandelC VHDL FPGA designs
,
Design, Automation and Test in Europe DATE˙02, p. 264
, Eds: Sciuto D., Kloos C. D.,
IEEE,
(Los Alamitos 2002)
,
Design, Automation and Test in Europe DATE˙02,
(Paris, FR, 04.03.2002-08.03.2002) [2002]
Matoušek R., Pohl Z., Kadlec Jiří, Tichý Milan, Heřmánek Antonín
:
Logarithmic arithmetic core based RLS LATTICE implementation
,
Design, Automation and Test in Europe DATE 02, p. 271
, Eds: Sciuto D., Kloos C. D.,
IEEE,
(Los Alamitos 2002)
,
Design, Automation and Test in Europe DATE 02,
(Paris, FR, 04.03.2002-08.03.2002) [2002]
