Bibliography

Conference Paper (international conference)

Dynamic runtime partial reconfiguration in FPGA

Matoušek Rudolf, Daněk Martin, Pohl Zdeněk, Kadlec Jiří

: ECMS 2003. 6th International Workshop on Electronics, Control, Measurement and Signals, p. 294-298 , Eds: Nouza J., Drábková J.

: Technical University, (Liberec 2003)

: ECMS 2003 /6./, (Liberec, CZ, 02.06.2003-04.06.2003)

: CEZ:AV0Z1075907

: IST-2001-34016, EU IST

: FPGA, runtine dynamic reconfiguration, VHDL

(eng): Runtime dynamic reconfiguration of FPGA devices has been an issue of the last decade. Although this feature permits more robust and more flexible designes and devices that posseses it are available on the market, it is not directly supported by the current design tools. This paper presents a simple design that uses true dymnamic reconfiguration for Atmel AT94K devices. The design has been implemented using a special feature of the currently available Figaro IDS5.2 tool in an innovative way.

: 09G, 09H

: JC