Bibliography

Journal Article

Lattice for FPGAs using logarithmic arithmetic

Kadlec Jiří, Matoušek Rudolf, Heřmánek Antonín, Líčko Miroslav, Tichý Milan

: Electronic Engineering vol.74, 906 (2002), p. 53-56

: CEZ:AV0Z1075907

: 33544, ESPRIT

: lattice Rls algorithm, FPGA, logarithmic arithmetic

(eng): Presented here are implementations of a complete RLS Lattice cores for Virtex. Their computational parallelism and ease of pipelining lead to easy mapping on FPGA. Internally, the computations are based on 32bit or 20bit logarithmic arithmetic (LNS). Compared are the 32bit LNS-SINGLE-ALU and 20bit LNS-QUAD-ALU versions. On Virtex XCV2000E-6, these use 27%, 54% or 40% of slices respectively and run at 50, 35 and 42 MHz on the Celoxica RC1000 board.

: 09G, 09H

: JC