Bibliografie

Conference Paper (international conference)

Logarithmic arithmetic core based RLS LATTICE implementation

Matoušek R., Pohl Z., Kadlec Jiří, Tichý Milan, Heřmánek Antonín

: Design, Automation and Test in Europe DATE 02, p. 271 , Eds: Sciuto D., Kloos C. D.

: IEEE, (Los Alamitos 2002)

: Design, Automation and Test in Europe DATE 02, (Paris, FR, 04.03.2002-08.03.2002)

: CEZ:AV0Z1075907

: LN00B096, GA MŠk

: logaritmic arithmetic core, FPGA, LNS

(eng): Presentation of HW implementation of a complete Recursive Least Square (RLS) LATTICE core for Virtex XCV800 device. The computational parallelism and ease of pipelining of LATTICE leads to easy mapping on FPGA. Demonstration of the active noise cancellation with four 20-bit parallel Logarithic Arithemtic ALUs on the XESS HW with Virtex XCV800-4.

: 09G, 09H

: JC