Bibliografie

Conference Paper (Czech conference)

Tuning and implementation of DSP algorithms on FPGA

Líčko Miroslav, Pohl Zdeněk, Matoušek Rudolf, Heřmánek Antonín

: Sborník příspěvků 9.ročníku konference MATLAB 2001, p. 226-230 , Eds: Procházka A., Uhlíř J.

: VŠCHT, (Praha 2001)

: MATLAB 2001 /9./, (Praha, CZ, 11.10.2001)

: AV0Z1075907

(eng): The article describes an algoritms development process for FPGA. It is shown on the example of the implementation of the QR RLS algorithm. To realise it means to perform operations such multiplication, division and square root.The research indicates, that the logarithmic arithemtic unit can reused for the real data type processing in some cases such a QR RLS algoritm.The developed prototype of logaritmic unit is tested on DSP algorithms using Matlab.

: 09G

: JC