Bibliografie

Conference Paper (international conference)

Implementation of Error-Feedback RLS Lattice on Virtex using logarithmic arithmetic

Albu F., Kadlec Jiří, Fagan A., Coleman J. N.

: Advances in Systems Science: Measurement, Circuits and Control. Proceedings, p. 517-521 , Eds: Mastorakis N. E., Pecorelli-Peres L. A.

: WSES Press, (Rethymno 2001)

: WSES International Conference on Circuits, Systems, Communications and Computers. CSCC 2001 /5./, (Rethymno, GR, 08.07.2001-15.07.2001)

: AV0Z1075907

: HSLA 33544, ESPRIT

: RLS Lattice, logarithmic number system

(eng): The LNS implementation of the Error-Feedback RLS Lattice algorithm in FPGA offers better speed than C30/C40 DSP floating-point and provides low- cost, efficient solution for different system on chip applications. We have demonstrated, that one can manage without a dedicated DSP processor.

: 09G

: JC