Bibliografie

Conference Paper (international conference)

Implementation of (Normalised) RLS Lattice on Virtex

Albu F., Kadlec Jiří, Softley Ch., Matoušek Rudolf, Heřmánek Antonín, Coleman J. N., Fagan A.

: Field-Programmable Logic and Applications. Proceedings, p. 91-100 , Eds: Brebner G., Woods R.

: Springer, (Berlin 2001)

: International Conference FPL 2001, (Belfast, IE, 27.08.2001-29.08.2001)

: AV0Z1075907

: HSLA 33544, ESPRIT

: field programmable gate array

(eng): The LNS implementation of the LRLS algorithms in a FPGA offers better speed than C30/C40 DSP floating-point and provides low-cost, efficient solution for different system-on-chip applications. The resulting RLS Lattice cores operate with 24-bit precision fixed-point input/output signals. Therefore, the internal conversion to the log domain and the internal LNS operation can be hidden from the user. This presented work provides significant speedup without any loss of precision.

: 09G, 09J

: JC