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7H10001
Honzík Petr, Bartosinski Roman, Daněk Martin, Kafka Leoš, Kohout Lukáš, Sýkora Jaroslav
:
Video Processing: Foreground Recognition in the ASVP Platform
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Smart Multicore Embedded Systems, p. 159-175
, Eds: Massimo T., Bertels K., Karlsson S., Pacull F. [2014]
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DOI:
10.1007/978-1-4614-8800-2_9
Bartosinski Roman, Daněk Martin, Kafka Leoš, Kohout Lukáš, Sýkora Jaroslav
:
The Architecture and the Technology Characterization of an FPGA-Based Customizable Application-Specific Vector Coprocessor (ASVP)
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Smart Multicore Embedded Systems, p. 45-77
, Eds: Massimo T., Bertels K., Karlsson S., Pacull F. [2014]
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DOI:
10.1007/978-1-4614-8800-2
Bartosinski Roman, Daněk Martin, Sýkora Jaroslav, Kohout Lukáš, Honzík P.
:
Foreground Detection and Image Segmentation in a Flexible ASVP Platform for FPGAs
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Proceedings of the 2012 Conference on Design & Architectures for Signal & Image Processing, p. 375-376
, Eds: Morawiec Adam, Hinderscheit Jinnie ,
Conference on Design & Architectures for Signal & Image Processing,
(Karlsruhe, DE, 23.10.2012-25.10.2012) [2012]
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Bartosinski Roman, Daněk Martin, Sýkora Jaroslav, Kohout Lukáš, Honzík P.
:
Video Surveillance Application Based on Application Specific Vector Processors
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Proceedings of the 2012 Conference on Design & Architectures for Signal & Image Processing, p. 248-255
, Eds: Morawiec Adam, Hinderscheit Jinnie ,
Conference on Design & Architectures for Signal & Image Processing,
(Karlsruhe, DE, 23.10.2012-25.10.2012) [2012]
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Sýkora Jaroslav, Bartosinski Roman, Kohout Lukáš, Daněk Martin, Honzík P.
:
Reducing Instruction Issue Overheads in Application-Specific Vector Processors
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Proceedings of the 15th Euromicro Conference on Digital System Design, DSD 2012, p. 600-607
, Eds: Niar Smail,
15th Euromicro Conference on Digital System Design,
(Cesme, TR, 05.09.2012-08.09.2012) [2012]
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Kadlec Jiří
:
In-circuit, Run-time Compiler of Finite State Machines for the UTIA EdkDSP Customizable Accelerators
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Fourth Friday Workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications, p. 32-33
, Eds: Silvano Cristina, Agosta Giovanni, Cardoso Joao,
DATE 2012 - Design Automation and Test in Europe conference and exhibition,
(Dresden, DE, 12.03.2012-16.03.2012) [2012]
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Sýkora Jaroslav, Kohout Lukáš, Bartosinski Roman, Kafka Leoš, Daněk Martin, Honzík P.
:
The Architecture and the Technology Characterization of an FPGA-based Customizable Application-Specific Vector Processor
,
Proceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, p. 62-67
, Eds: Raik, J. , Stopjaková, V. , Jenihhin, M. , Vierhaus, H., T. , Pleskacz, W. , Ubar, R. ,
2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems,
(Tallinn, EE, 18.04.2012-20.04.2012) [2012]
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DOI:
10.1109/DDECS.2012.6219026
Honzík P., Kadlec Jiří
:
Dynamic Placement Applications into Self Adaptive Network on FPGA
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2011 IEEE 14th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS 2011), p. 453-456
, Eds: Vierhaus Heinrich T. , Pawlak Adam, Schölzel Mario, Steininger Andreas, Kraemer Rolf, Raik Jaan,
14th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2011),
(Cottbus, DE, 13.04.2011-15.04.2011) [2011]
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DOI:
10.1109/DDECS.2011.5783135
Bartosinski Roman
:
The LD-RLS algorithm with directional forgetting implemented on a vector-like hardware accelerator
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ICASSP 2011: IEEE International Conference on Acoustics, Speech, and Signal Processing, p. 1657-1660,
ICASSP 2011: IEEE International Conference on Acoustics, Speech, and Signal Processing,
(Praha, CZ, 22.05.2011-27.05.2011) [2011]
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DOI:
10.1109/ICASSP.2011.5946817
